OpenRTLSet: A Fully Open-Source Dataset for Large Language Model-based Verilog Module Design
Quick Answer
OpenRTLSet is the largest open-source dataset for hardware design, featuring over 131,000 Verilog code samples.
Quick Take
It enables fine-tuning of language models like Qwen and Granite for Verilog code generation, demonstrating superior performance in hardware design tasks through open-source methodologies.
Key Points
- Dataset includes 102k Verilog modules from GitHub and 29k from translations.
- Paired natural language descriptions generated using DeepSeek-R1 model.
- Explores quantization techniques like INT4 and BF16 for performance.
- Supports fine-tuning for various language model families.
- Establishes a foundation for accessible research and commercial use.
Paper Resources
Source Excerpt
OpenRTLSet introduces the largest fully open-source dataset for hardware design, offering over 131,000 diverse Verilog code samples to the research community and industry. Our dataset uniquely combines Verilog code from GitHub repositories (102k modules), VHDL translations (5k modules), and synthesizable C/C++ translations (24k modules), all freely accessible without proprietary restrictions. Using the reasoning model DeepSeek-R1, we generated paired natural language descriptions for each code s
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