An MLIR-Based Compilation Method for Large Language Models
Quick Answer
This paper introduces an MLIR-based compilation method for large language models (LLMs) that addresses challenges in deploying them on specialized hardware.
Quick Take
It utilizes TopOp and TpuOp dialects for model representation and scheduling, implemented in the TPU-MLIR compiler, supporting various generative models like Qwen and Llama with multiple quantization forms.
Key Points
- MLIR-based method improves deployment of on specialized hardware.
- TopOp represents model semantics, while TpuOp handles hardware-specific decisions.
- Transformer layers are split into three stages for efficient static compilation.
- Supports generative models like Qwen, Llama, and MiniCPM-V series.
- Facilitates multiple quantization methods including GPTQ and AWQ.
DeepSignal Analysis
What happened
The paper presents a compilation method for large language models (LLMs) using MLIR, addressing challenges in deploying these models on specialized hardware. It employs TopOp and TpuOp dialects for model representation and scheduling, implemented in the TPU-MLIR compiler, and supports various generative models with multiple quantization forms.
Key evidence
- The method utilizes TopOp as a high-level graph dialect to express model semantics, independent of the source framework and target chip.
- TpuOp serves as the target hardware dialect, incorporating chip-specific decisions such as quantization and memory layout.
- The compilation process involves lowering a model from TopOp to TpuOp and generating a deployable binary, supporting models like Qwen and Llama.
Why it matters
This method is significant as it addresses the dual challenges of model importation into a compiler-friendly format and efficient scheduling for autoregressive inference. By optimizing these aspects, the approach could enhance the deployment efficiency of LLMs on specialized hardware, which is crucial for advancing AI applications.
What to watch
Paper Resources
📖 Reader Mode
~2 min readAbstract:Large Language Models (LLMs) have become the dominant workload on modern AI accelerators, yet deploying them on specialized hardware still faces two core challenges: how to import a trained model into a compiler-friendly intermediate representation, and how to efficiently schedule the autoregressive inference loop under limited on-chip memory. This paper presents an MLIR (Multi-Level Intermediate Representation) based compilation method for large language models, illustrated using two dialects of operators, TopOp and TpuOp. TopOp serves as a high-level graph dialect that is independent of both the source framework and the target chip, and is responsible for expressing model semantics; TpuOp serves as the target hardware dialect, carrying chip-related decisions such as quantization, layer groups, and memory layout. A model is first represented as TopOp, then lowered layer by layer to TpuOp, and finally a deployable binary is generated. In addition, each Transformer layer is split into three stages for static compilation: prefill, prefill_kv (prefill with historical key-value cache), and decode, so as to accommodate the different computational characteristics of prompt-parallel processing and per-token generation. The method has been implemented in the TPU-MLIR compiler{this https URL} and the LLM-TPU deployment project\footnote{this https URL}, supporting a variety of generative models including the Qwen, Llama, InternVL, and MiniCPM-V series, as well as multiple quantization and deployment forms such as GPTQ, AWQ, and AutoRound.
| Subjects: | Computation and Language (cs.CL) |
| Cite as: | arXiv:2607.15865 [cs.CL] |
| (or arXiv:2607.15865v1 [cs.CL] for this version) | |
| https://doi.org/10.48550/arXiv.2607.15865 arXiv-issued DOI via DataCite (pending registration) |
Submission history
From: Pengchao Hu [view email]
[v1]
Fri, 17 Jul 2026 11:24:45 UTC (385 KB)
— Originally published at arxiv.org
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