GoGoTB: Agentic RTL Verification with Specification-Grounded Coverage Closure
Quick Answer
GoGoTB introduces an agentic framework for RTL verification, achieving 100% environment generation success and high coverage metrics (98.4% line, 97.2% branch) without human intervention.
Quick Take
This addresses critical gaps in existing -based verification methods by integrating specification-grounded coverage closure and an evolvable knowledge system.
Key Points
- GoGoTB consists of three subsystems: execution control, knowledge system, and coverage framework.
- Achieved 100% environment generation success on 8 RTL designs without human intervention.
- Coverage metrics include 98.4% line, 97.2% branch, and 83.2% functional coverage.
- Addresses interface mismatches and disconnects in existing LLM-based verification approaches.
- No prior work has achieved similar verification environment completeness on these benchmarks.
DeepSignal Analysis
What happened
GoGoTB is a newly introduced framework for register transfer level (RTL) verification that operates without human intervention. It has achieved a 100% success rate in environment generation and high coverage metrics, including 98.4% line and 97.2% branch coverage, across eight RTL designs.
Key evidence
- GoGoTB achieves 100% environment generation success and high coverage metrics of 98.4% line and 97.2% branch coverage.
- The framework integrates three subsystems: an agentic execution control layer, an evolvable knowledge system, and specification-grounded coverage closure.
- GoGoTB was tested on eight RTL designs, demonstrating its capability to generate a complete verification environment without human intervention.
Why it matters
The introduction of GoGoTB addresses significant limitations in existing LLM-based verification methods, which often fail to maintain context across components. By ensuring that coverage is connected to specification requirements, GoGoTB could reduce the risk of undetected interface mismatches and costly bugs in integrated circuits.
What to watch
Paper Resources
Source Excerpt
Functional verification dominates integrated circuit (IC) front-end engineering effort, and a single missed bug that escapes to silicon can trigger a costly respin. Recent (LLMs) offer new opportunities to automate this process, yet existing LLM-based approaches generate each component through independent single-turn calls with no shared context, leaving interface mismatches undetected and reported coverage disconnected from specification requirements. To address these chal
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