SCALE: Self-Supervised Constraint-Aware Layout GEneration for Local P&R DRV Fixing at Advanced Nodes
Quick Answer
SCALE introduces a self-supervised layout generation framework for fixing local design-rule violations (DRV) in sub-2nm semiconductor nodes, achieving a 12-25% improvement in solve rates for complex violations.
Quick Take
By leveraging a fine-tuned language model, it generates DRC-annotated layout-violation pairs, enhancing rule-aware geometric guidance for DRV repair, validated by an industrial DRC checker.
Key Points
- SCALE addresses complex rule interactions and dense multi-layer routing geometries.
- The framework uses a fine-tuned language model to reconstruct masked polygons.
- It produces DRC-annotated layout-violation pairs for further model training.
- Achieves up to 97% solve rates on 100 real sub-2nm DRV cases.
- Improves state-of-the-art agents' performance by 12-25%.
DeepSignal Analysis
What happened
SCALE is a new framework designed to address local design-rule violations (DRV) in semiconductor manufacturing at sub-2nm nodes. It utilizes a self-supervised layout generation process that improves the solve rates for complex violations by 12-25%, validated by an industrial DRC checker.
Key evidence
- SCALE employs a fine-tuned language model to reconstruct polygons from surrounding context, enhancing the understanding of layout violations.
- The framework generates DRC-annotated layout-violation pairs, which are used to fine-tune a domain-adapted DRC-VLM for improved guidance.
- SCALE achieved a solve rate improvement of up to 97% on 100 real sub-2nm cases, addressing various types of violations.
Why it matters
As semiconductor technology progresses towards smaller nodes, the complexity of design-rule violations increases, making efficient fixing methods crucial. SCALE's approach leverages advanced AI techniques to enhance the layout generation process, potentially leading to more efficient manufacturing workflows and reduced time-to-market for advanced semiconductor products.
What to watch
Paper Resources
Source Excerpt
As semiconductor manufacturing advances toward sub-2nm nodes, local place-and-route (P&R) design-rule violation (DRV) fixing is increasingly limited by complex rule interactions, dense multi-layer routing geometries, and foundry-specific constraints. While (LLMs) have recently demonstrated strong capabilities in EDA scripting and documentation, their application to visual layout understanding remains largely unexplored: diagnosing DRC violations from layout imagery demands
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